Direct memory access controller (DMA) are typically used in microprocessor systems, integrated microcontrollers, etc. DMA controllers are used to perform a data transfer from and to memory to and from a peripheral independently from the central processing unit of the computer system. To this end, a DMA controller can be seen as a second programmable processing unit with limited capabilities. Generally, a DMA controller is instructed to transfer a specific amount of data from a source location to a destination location. The source can be within a memory, for example, a data memory of a microcontroller, memory of a peripheral, or data generated by or accessible within a peripheral, such as an analog to digital converter, a port, a capture compare unit, etc. The destination can also be within a memory, thus, allowing high speed transfers within a memory device of a computer system or microcontroller. However, the destination can also be a peripheral, such as a digital to analog converter, a port, etc. To transfer data from a source to a destination the DMA controller must receive the respective source and destination addresses. In addition, each transfer length needs to be specified. To this end, the DMA controller needs to receive either the length of the data transfer or the start and end address of the data to be transferred.
Moreover, DMA controllers are used to support the central processing unit (CPU) in a system, in particular for lengthy data transfers. The CPU is then free to perform other functions. However, CPU and DMA controller share the same memory bus system. Thus, to prohibit any type of collision between CPU and DMA when accessing the bus, which may stall the DMA by the CPU, the DMA usually has priority over the CPU which is prohibited from accessing the memory bus while a transfer is in progress. Even though the CPU can perform other functions that do not involve an access to the shared memory bus, this DMA priority may limit the flexibility of a system. Thus, there exists a need for a improved system having a DMA controller.